1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and in particular to an improved method for manufacturing a Metal-Oxide-Semiconductor Field Effect Transistor (“MOSFET”) employing a tungsten gate wherein the oxidation of a barrier metal film and a metal layer is preventing using an EXtended Trench Isolation GATE (“EXTIGATE”) structure to improve yield and reliability of the device.
2. Description of the Background Art
As the integration density of a semiconductor device is increased, the size of each device is decreased. In order to reduce of the size of the device, overall design rule for a gate electrode, a source/drain region or contacts thereof of MOSFET is decreased. The width of the gate electrode is inversely proportional to electrical resistance such that when the width of the gate electrode is decreased by 1/n times, the electrical resistance thereof is increased by n times. The increase in the electrical resistance reduces the operating speed of the semiconductor device. One of the methods proposed for reducing the electrical resistance of the gate electrode is using a polycide which is a stacked structure of a polysilicon and a silicide having stable interface characteristics for the gate electrode.
FIGS. 1a through 1e are cross-sectional diagrams illustrating a conventional method for manufacturing semiconductor device including an EXTIGATE MOSFET.
Referring to FIG. 1a, a gate oxide film (not shown), a polysilicon film (not shown), an intermediate oxide film (not shown) and a first nitride film (not shown) are sequentially deposited on a semiconductor substrate 10. The first nitride film, the intermediate oxide film, the polysilicon film and the gate oxide film are patterned via a photo-etching process using a device isolation mask to form a stacked structure of a gate oxide film pattern 11, a polysilicon film pattern 12, a intermediate oxide film 13 and a first nitride film pattern 14 exposing device isolation region of the semiconductor substrate 10. Thereafter, the exposed portion of the semiconductor substrate 10 is etched by a predetermined depth to form a trench 15.
Referring to FIG. 1b, an oxide film for device isolation film is deposited on the entire surface of the structure. The oxide film for device isolation film is then planarized via a chemical mechanical polishing (“CMP”) process until the first nitride film pattern 14 is exposed to form a device isolation film 16.
Now referring to FIG. 1c, the first nitride film pattern 14 is removed. A p-well 17 and an n-well 18 are formed in predetermined regions of the semiconductor substrate 10 via an ion implant process using a well mask and a drive-in process.
Referring to FIG. 1d, the entire surface is planarized to expose the polysilicon film pattern 12. A barrier metal film 19, a metal layer 20 and a second nitride film 21 are sequentially formed on the entire surface of the structure.
Referring to FIG. 1e, the second nitride film 21, the metal layer 20, the barrier metal film 19 and the polysilicon film pattern 12 are patterned via a photoetching process using a word line mask to form a gate electrode. Thereafter, an oxide film 22 is formed on a sidewall of the polysilicon film pattern 12. A nitride film (not shown) is then formed on the entire surface and etched back to form an insulating spacer 23.
Thereafter, although not shown, subsequent processes such as a formation process of a source/drain region are performed.
In accordance with the above-described method for manufacturing semiconductor device including the EXTIGATE MOSFET, although the method was proposed to overcome the disadvantage of a conventional Shallow Trench Isolation (“STI”) method, voids are generated during the deposition process of oxide film for device isolation film due to a large step difference between the trench and the first nitride film. In addition, since the barrier metal film and the metal layer are deposited directly on the device isolation film, oxidation occurs, thereby increasing the resistance of the gate electrode. Moreover, the exposure of the barrier metal film and the metal layer during the oxidation of the sidewall of the polysilicon film pattern accelerates the oxidation of the barrier metal film and the metal layer, resulting in insufficient thickness of the oxide film on the sidewall to cause electrical short between layer during subsequent processes. These disadvantages result in degradation of the yield and reliability of the device.